Field effect transistors (FETs) using a ferroelectric layer is proposed as a nonvolatile memory device. An example of an FET using a PZT (PBZr.sub.x Ti.sub.1-x O.sub.3) is shown in FIG. 13. The FET 12 shown in FIG. 13 is a kind of FET having a structure so called MFMIS (Metal Ferroelectric Metal Insulator Silicon). The FET 12 is formed by means of disposing a gate oxidation layer 4, a floating gate 6, a ferroelectric layer 8, and a control gate 10 in that order on a channel region CH formed in a semiconductor substrate 2.
The polarization of the ferroelectric layer 8 is turned over when a positive voltage +V is applied to the control gate 10 while grounding the substrate 2 of the FET 12 (an N channel substrate). Negative electric charges are established in the channel region CH as a result of a remanence polarization remaining in the ferroelectric layer 8 even when the positive voltage +V no longer is applied to the control gate 10. A condition that the negative electric charges are in the channel region CH corresponds to data "1".
On the contrary, occurrence of another polarization reversal in the opposite polarity is observed when a negative voltage -V is applied to the control gate 10. Positive electric charges are generated in the channel region CH as a result of a remanence polarization remaining in the ferroelectric layer 8 even when the negative voltage -V no longer is applied to the control gate 10. Another condition that the positive electric charges are in the channel region CH corresponds to data "0". Either of data "1" or data "0" is stored in the FET 12 by carrying out the procedures described above.
In order to read out the data being stored therein, a readout voltage Vr is applied to the control gate 10. The readout voltage Vr is set at a value between the threshold voltage Vthl of the FET 12 which is defined when the data "1" is stored and the threshold voltage VthO of the FET 12 which is defined when the data "0" is stored. Judgement of the stored data, either in "1" or "0" can be carried out by detecting whether a drain current predetermined flows or not when the readout voltage Vr is applied to the control gate 10. The stored data is never erased after reading out the data.
Thus, nondestructive readout can be carried out using the FET including a ferroelectric layer. Further, such device is capable of composing one memory cell.
However, the FET using the ferroelectric described above has the following problems to be resolved. The FET 12 is considered in a condition that a capacitor Cf (capacity Cf) which includes the ferroelectric layer 8 and a capacitor Cox (capacity Cox) having the gate oxidation layer 4 is connected in series during the writing (see FIG. 2). Under the circumstances, a divided voltage Vf defined by the following equation is applied to the capacitor Cf when a voltage (equal to either of +V or -V) is applied at a point located between the substrate 2 and the control gate 10, EQU Vf=Cox/(Cf+Cox).multidot.V.
On the other hand, in order to cause the polarization reversal of the ferroelectric layer 8 during the writing, the divided voltage Vf needs to be a large value. And, the capacitance of the capacitor Cf should be a small value relative to that of the capacitor Cox as in is clear from the equation shown in above. The relative dielectric constant (200 to 1,000) of the PZT composing the ferroelectric layer 8 is much higher than the relative dielectric constant (3.9) of the Sio.sub.2 which composes the gate oxidation layer 4.
Consequently, it is difficult to increase the divided voltage Vf shown above. It is therefore, not easy to cause polarization reversal of the ferroelectric layer 8 during the writing. The melting point of PZT is at a low temperature (800 to 900.degree. C.) because PZT contains Pb. This leads to lattice defects in an FET requiring heat treatment after forming a ferroelectric layer. A similar problem to PZT may be observed in a ferroelectric material using bismuth (Bi).